ISSCC 2010 Advance Program

ISSCC 2010 Advance Program

5.7 A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS

A 567mm2 processor on 45nm CMOS integrates 48 IA-32 cores and 4 DDR3 channels in a 6×4 2D-mesh network. Cores communicate through message passing using 384KB of on-die shared memory. Finegrain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. As performance scales, the processor dissipates between 25W and 125W.

これが、Intel の Single-chip Cloud Computer に関する発表のようだ。

5.5 A Wire-Speed PowerTM Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads

A 64-thread simultaneous multi-threaded processor uses architecture and implementation techniques to achieve high throughput at low power. Included are static VDD scaling, multi-voltage design, clock gating, multiple VT devices, dynamic thermal control, eDRAM and low-voltage circuit design. Power is reduced by >50% in a 428mm2 chip. Worst-case power is 65W at 2.0GHz, 0.85V.

IBM 版 Niagara といったところか?

5.3 A 45nm 37.3GOPS/W Heterogeneous Multi-Core SoC

A 648MHz 153.8mm2 45nm CMOS SoC integrates eight general-purpose CPUs, four dynamically reconfigurable processors, two 1024-way matrix-processors, peripherals and interfaces. Using core enhancement, DDR3-I/F improvement and clock buffer deactivation, this SoC achieves 37.3GOPS/W at 1.15V.

ルネサスのヘテロジニアスマルチコアチップ。

　- 汎用プロセサ×8
　- リコンフィギュアラブルプロセサ×4
　- 1024wayマトリックスプロセサ×2

と、かなり複雑なものになっている。