IBMのl'IDRIS講演資料

Multicore and Massive Parallelism at IBM (PDF)

POWER7/7+
- 45/32nm
- 8コア/ダイ
- ｵﾝチップeDRAM

ASC Sequoia
- 18コア/チップ (2コアは通信用?)

チップの開発の方向性
- Programming Intrusiveness
　+ Single-thread program
　+ Java program
　+ Annotated program
　+ Explicit threads
　+ Parallel languages
- Compiler Innovations
　+ Traditional Compiler
　+ Parallelizing Compiler
　+ JIT Parallelizing Compiler
　+ Directives + Compiler
　+ Parallel Language Compiler
- Hardware Innovations
　+ Speculative threads
　　　Single-thread program, Traditional Compiler との組み合わせ
　+ Assist threads
　+ Functional threads
　　　Parallel languages, Parallel Language Compiler との組み合わせ

IBMの3つのアプローチ
- Blue Gene:
　　Maximize Flops Per Watt
　　with Homogeneous Cores
　　by reducing Single Thread Performance
- Power/PARCS:
　　Maximize Productivity and Single Thread
　　Performance with Homogeneous Cores
- Roadrunner:
　　Use Heterogeneous Cores and
　　an Accelerator Software Model
　　to Maximize Flops Per Watt
　　and keep High Single Thread Performance